Critical Paths Selection for Delay Faults

Extended Abstract Right timing of complex digital circuits and systems in nanotechnology need careful design steps and testing. Incorrect timing can be caused during design or manufacturing processes. Incorrect timing is manifested as delay faults. The delay faults in digital circuit testing are more and more important due to huge number of gates and lines integrated on a chip specifically in nanotechnologies. Some test vectors have to be prepared for delay faults testing depending on fault models. Various fault models exist for test vectors generation from which the gate delay fault model, the transition fault model and the path delay fault model are basic models for time specification testing. The paths delay faults are crucial for nanotechnologies based on their tiny geometries in digital integrated circuits. These faults are tested only via selected critical paths in a tested digital circuit because huge number of paths exists in its structure. Nowadays, the critical paths are specified e.g. by static timing analysis (STA), dynamic timing analysis (DTA) and others. During last decade new aspects have been recognized in critical paths selection. Many factors such as multiple input switching, power supply noise, type of propagated signal edge (rising, falling) and others affecting the signal delay propagation and thus they can increase path criticality (Wu et al., 2010). The impact of each parameter to the path delay faults has been solved and published in some papers by (Dobai et al., 2010), (Wu et al., 2008) and (Metzler et al., 2013) but their joint effects should be also investigated. The paper presents a new method and a new formula for evaluation of paths criticality. The method contributes to higher delay fault coverage in digital circuits. Experiments over benchmark circuits have proved effectiveness of the method and its implementation to an automatic system for critical paths selection based on multiple parameters effects. A new general method for critical path selection has been developed and implemented based on influence on multiple parameters, STA, DFT and new defined formula. The main idea is sort a list of critical paths founded by STA using the new defined requirement – path criticality for increasing path delay fault coverage. Path criticality cp based on multiple parameters is expressed by formula: